Volume 34 Issue 1
Jan.  2014
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Zhou Li, An Junshe, Xie Yan, Li Xianqiang, Cao Song. Design of a 1553B IP core based on ASIC technology[J]. Journal of Space Science, 2014, 34(1): 127-136. doi: 10.11728/cjss2014.01.127
Citation: Zhou Li, An Junshe, Xie Yan, Li Xianqiang, Cao Song. Design of a 1553B IP core based on ASIC technology[J]. Journal of Space Science, 2014, 34(1): 127-136. doi: 10.11728/cjss2014.01.127

Design of a 1553B IP core based on ASIC technology

doi: 10.11728/cjss2014.01.127
  • Received Date: 2013-01-23
  • Rev Recd Date: 2013-10-23
  • Publish Date: 2014-01-15
  • It is a problem to miniaturize space avionics when we use traditional 1553B bus interface chips. To solve this problem, design of an ASIC chip for spacecraft integrated avionics is proposed. The design of a 1553B IP core with independent intellectual property in this chip is described in detail. The 1553B IP core includes the bus controller module, the remote terminal module, the Manchester decode and encode module, the shared RAM, the RAM arbitration module, the AXI bus slave interface module, the channel select module and the timer module. Each module is introduced. The top-down designing method is used and the program is described by Verilog hardware description language. The 1553B IP core design is tested and verified by the functional simulation, the ASIC system simulation and FPGA test. DDC's 1553B test board is used to test the IP core. The test results indicate that the 1553B IP core design is reasonable. The design of 1553B IP core has good performance in reliability, portability, real-time and less resource occupancy.

     

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