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28 nm体硅工艺FPGA BRAM脉冲激光试验及翻转特性

薛国凤 周昌义 安军社 吴昊 王天文

薛国凤, 周昌义, 安军社, 吴昊, 王天文. 28 nm体硅工艺FPGA BRAM脉冲激光试验及翻转特性[J]. 空间科学学报, 2024, 44(6): 1147-1154. doi: 10.11728/cjss2024.06.2024-0007
引用本文: 薛国凤, 周昌义, 安军社, 吴昊, 王天文. 28 nm体硅工艺FPGA BRAM脉冲激光试验及翻转特性[J]. 空间科学学报, 2024, 44(6): 1147-1154. doi: 10.11728/cjss2024.06.2024-0007
XUE Guofeng, ZHOU Changyi, AN Junshe, WU Hao, WANG Tianwen. SEE Upset Characteristics of BRAM in 28 nm Bulk FPGA by Pulsed Laser Test (in Chinese). Chinese Journal of Space Science, 2024, 44(6): 1147-1154 doi: 10.11728/cjss2024.06.2024-0007
Citation: XUE Guofeng, ZHOU Changyi, AN Junshe, WU Hao, WANG Tianwen. SEE Upset Characteristics of BRAM in 28 nm Bulk FPGA by Pulsed Laser Test (in Chinese). Chinese Journal of Space Science, 2024, 44(6): 1147-1154 doi: 10.11728/cjss2024.06.2024-0007

28 nm体硅工艺FPGA BRAM脉冲激光试验及翻转特性

doi: 10.11728/cjss2024.06.2024-0007 cstr: 32142.14.cjss.2024-0007
基金项目: 国家重点研发计划项目资助(2022YFF0503900)
详细信息
    作者简介:
    • 薛国凤 女, 1984年6月出生于陕西省西安市, 现为中国科学院国家空间科学中心高级工程师, 主要研究方向为空间综合电子技术. E-mail: xueguofeng@nssc.ac.cn
    通讯作者:
    • 周昌义 男, 1965年8月出生于湖北省汉川市, 现为中国科学院国家空间科学中心研究员, 博士生导师, 主要研究方向为空间综合电子技术. E-mail: zhoucy@nssc.ac.cn
  • 中图分类号: V524

SEE Upset Characteristics of BRAM in 28 nm Bulk FPGA by Pulsed Laser Test

  • 摘要: 针对SRAM型FPGA内部BRAM在轨出现翻转错误以及如何有效进行容错设计的问题, 提出了测试BRAM空间单粒子效应和多位翻转图样的方法. 多位翻转图样可以表征单次单粒子事件导致的BRAM中相邻单元的翻转特征, 进而用于分析逻辑字内是否存在多位翻转. 以XC7K410T-FFG900为研究对象, 分析其内部资源的组织结构, 采用脉冲激光试验测试BRAM的翻转特性. 通过试验测得FPGA内BRAM的翻转阈值以及在不同激光能量下的翻转截面, 并分析得到BRAM在不同能量照射下的多位翻转图样. 试验结果表明, BRAM中单个单元翻转所占比例随激光能量的增加而降低, 而多单元翻转所占比例随激光能量的增加呈上升趋势. BRAM在不同脉冲激光能量下可产生2 bit到11 bit的多单元翻转, 但通过错误注入试验验证, 该多单元翻转在单个字或者字节内并无多位翻转问题. 研究结果为提高SRAM型FPGA在航天应用中的可靠性提供了试验支持, 并依据BRAM的翻转特性给出了SRAM型FPGA在轨加固方法和建议.

     

  • 图  1  Kintex-7系列FPGA资源结构

    Figure  1.  Structure of Kintex-7 FPGA resources

    图  2  BRAM在frame中的组织结构

    Figure  2.  Layout of BRAM in frames

    图  3  试验系统原理

    Figure  3.  Diagram of the experiment system

    图  4  脉冲激光试验扫描路径

    Figure  4.  Pulsed laser scan route

    图  5  脉冲激光试验现场

    Figure  5.  XCF7 K410 T test board during pulsed laser testing

    图  6  脉冲激光试验流程

    Figure  6.  Flowchart of pulsed laser test

    图  7  BRAM 的SEU翻转截面

    Figure  7.  Cross section of BRAM SEU

    图  8  450 pJ时BRAM翻转位分布

    Figure  8.  Distribution of upset in BRAM under 450 pJ energy

    图  9  BRAM物理布局

    Figure  9.  Physical layout of BRAM

    图  10  BRAM中SCU和MCU的占比

    Figure  10.  Proportion of SCU and MBU in BRAM

    图  11  BRAM的2 bit MCU图样

    Figure  11.  2 bit MCU upset pattern in BRAM

    图  12  500 pJ时BRAM 中的MCU翻转图样

    Figure  12.  MCU upset patterns in BRAM under 500 pJ energy

    图  13  不同能量下BRAM中的最大MCU翻转图样

    Figure  13.  Maximum MCU upset pattern in BRAM under different energy

    图  14  带ECC及系统维护功能的BRAM模块

    Figure  14.  Diagram of BRAM control logic with ECC and system maintenance

    图  15  故障注入仿真波形

    Figure  15.  Simulation waveform of error injecting

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出版历程
  • 收稿日期:  2024-01-09
  • 修回日期:  2024-03-01
  • 网络出版日期:  2024-03-16

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