Software–Hardware Co-Designed Fault-Tolerance and Optimization for a Spaceborne CNN FPGA Accelerator

To address the dual challenges of limited on-board resources and radiation reliability requirements in spaceborne computing platforms, this paper proposes an FPGA-based software–hardware co-designed fault-tolerant accelerator for convolutional neural network inference. The accelerator employs INT8/FP16 mixed-precision quantization to improve computational density and execution efficiency, while a hierarchical software–hardware fault-tolerance scheme is introduced to enhance system reliability. Specifically, at the software level, an asymmetric dual-branch architecture together with a confidence evaluator is adopted to suppress disturbances in the data path. At the hardware level, triple modular redundancy (TMR) is applied to critical control logic, including the controller and finite state machine (FSM), to mitigate the impact of single-point faults in the control path. Experimental results show that, when deploying the VGG-16 network on the XC7VX690T platform, the proposed accelerator achieves a throughput of 226.4 GOPS, an inference latency of 136.52 ms, and an average effective execution efficiency of 81.5% for the underlying computing array. Under fault injection conditions, the system still maintains high classification accuracy, demonstrating that the proposed method can satisfy the requirements for efficient and reliable intelligent inference in spaceborne edge computing scenarios.